1. Field of the Invention
The present invention generally relates to means for fetching, and storing data stored in a recirculating loop memory array and, more particularly, to shift register means for accomplishing those functions with speed and economy of structure.
2. Description of the Prior Art
In charge coupled device (CCD) memory arrays, multiple CCD loops are organized so as to be accessible via a single input pin and via a single output pin. Accordingly, the loops are accessed in serial succession. In those cases where the entire array is to be initialized to a predetermined state or tested to verify that the stored data is correct, sufficient time must be allocated to complete the serial accessing of the CCD loops. The required time increases objectionably as the CCD memory array increases in density to include larger numbers of individual loops. Direct parallel accessing of the individual CCD loops, on the other hand, permits much more rapid initialization, but only at the expense of requiring unacceptably large numbers of input-output (I/O) pins.
Indirect parallel accessing of interior logic circuit points has been achieved via I/O pins according to a technique described in U.S. Pat. No. 3,783,254 to E. B. Eichelberger for "Level Sensitive Logic System", issued Jan. 1, 1974 and assigned to the present assignee and in related U.S. Pat. Nos. 3,761,695 and 3,784,907 to the same inventor. Briefly, clocked dc latches are provided at logic network nodes to be tested and additional circuitry is included to selectively connect the latches into a functional shift register. A predetermined pattern of binary ones and zeros can then be introduced serially into the shift register latches where they are retained for later use as parallel inputs to the logic network nodes to be tested. Additional clocked dc latches are provided at other logic network nodes to receive the signals representing the test results produced by the test signals introduced by the first clocked dc latches. Once the test results are stored in the second clocked dc latches, further circuitry connects the latches into a functional shift register which enables the test results to be shifted out. This technique, however, is not well suited for the dynamic testing of data stored within CCD loops within a memory array.
Copending patent application Ser. No. 163,374, now U.S. Pat. No. 4,313,199 for "Recirculating Loop Memory Array Fault Locator", filed June 26, 1980, in the names of F. J. Aichelmann, Jr. et al and assigned to the present assignee, discloses a technique for quickly determining (within designated subdivisions or partitions of recirculating type memory arrays) the locations of faulty bits received from the constituent recirculating type memory elements comprising the array. All loop memory elements are initialized to a predetermined condition for testing purposes by the loading of all loops with the same test data. The stored data is verified by means of a number of comparison gates. A distinctive signal is generated by a given comparison gate in the event that any one or more bits of the data received from one or more of the loops associated with the given comparison gate is non-identical to the data bits from all other associated loops. The output signals produced by the comparison gates are sensed in serial succession to locate the array subdivision containing any faulty elements. In one embodiment of the invention, a latch is provided at the output of each comparison gate. Each latch is set to store the information that one or more bits are faulty from the loops associated with that comparison gate. The latches are then sensed at logic speeds. The latches, however, perform no role in the storing of data within the recirculating loops nor do they participate in the fetching of data from the individual loops.